Modern semiconductor switches using Wide Band Gap (WBG) technologies, including SiC and GaN, and even advanced MOSFETs and some IGBTs are capable of extremely fast switching. This reduces dissipation during switching transitions, allowing higher frequency operation at high efficiency. This results in higher power density, smaller passive components, and lower cost. However, there is a downside of increased EMI and stress on gate drive insulation systems due to high dV/dt and di/dt levels.
Figure 1 shows a typical gate drive circuit for an IGBT applying a positive voltage between 5V and 20V to switch the device ON and 0V to switch it OFF. Statically, this circuit also works perfectly well for enhancement mode Si MOSFETs and WBG devices in SiC and GaN technology – in all cases the device is reliably off with a continuous 0V applied to the gate.
Fig. 1: Simplistic gate drive circuit
However, problems occur when the device is switched fast and parasitic capacitive and inductive elements, as shown in Figure 2, come into play.
Fig. 2: Gate drive with parasitic elements included
If we take the example of a di/dt figure for drain-source current of 10A/ns, which is feasible with state-of-the-art GaN devices, and a source inductance of 15nH, according to V = - L di/dt, 150V appears across the inductor. On switch-off, this voltage drags the source negative, opposing the gate drive, and on switch-on, the direction is positive, again opposing the gate drive. The consequence can be loss of efficiency and even damage due to spurious turn-on causing shoot-through. 15nH may seem large but represents only about 25mm of PCB track.
Even a PCB via has an inductance of about 1.2nH, producing a 12V transient. In practice, at these high di/dt levels, only chip-scale packaging is practical with Kelvin connections to the gate and source for the gate drive. Driving the gate with a negative voltage for the off-state helps when some inductance cannot be avoided. In real circuits such as push-pull or full-bridges in inverters or motor control, two low-side devices often share a common return for source and gate drive current, as shown in Figure 3.
Fig. 3: Low-side devices sharing common grounds
Now, Kelvin connections are not possible because there are two drivers, each with its own return. The two driver grounds and two emitter (source) connections must be connected together. If this connection point is physically located at Powergnd 1, near the left-hand switch, the right-hand switch will experience greater source connection inductance than the left. This results in asymmetrical switching, potential EMI, and possible damage due to induced voltages across the inductance.
For symmetry, the point 'Powergnd 2' is the only viable option, but it remains a poor compromise. In this configuration, both sources have equal—but large—connection inductances in the gate drive loop, especially in high-power electronic systems where the devices may not be physically close together. A solution is to provide isolated signals and power supplies to the two gate drivers as shown in Figure 4. This is often achieved using a gate driver DC/DC converter. Now the driver signal and power returns can connect directly to their respective device emitters (sources), excluding most external inductances from the drive loops.
Fig. 4: Gate drives incorporating signal and power isolation with Kelvin connections
Figure 1 shows a typical gate drive circuit for an IGBT applying a positive voltage between 5V and 20V to switch the device ON and 0V to switch it OFF. Statically, this circuit also works perfectly well for enhancement mode Si MOSFETs and WBG devices in SiC and GaN technology – in all cases the device is reliably off with a continuous 0V applied to the gate.
Fig. 1: Simplistic gate drive circuit
However, problems occur when the device is switched fast and parasitic capacitive and inductive elements, as shown in Figure 2, come into play.
Fig. 2: Gate drive with parasitic elements included
If we take the example of a di/dt figure for drain-source current of 10A/ns, which is feasible with state-of-the-art GaN devices, and a source inductance of 15nH, according to V = - L di/dt, 150V appears across the inductor. On switch-off, this voltage drags the source negative, opposing the gate drive, and on switch-on, the direction is positive, again opposing the gate drive. The consequence can be loss of efficiency and even damage due to spurious turn-on causing shoot-through. 15nH may seem large but represents only about 25mm of PCB track.
Even a PCB via has an inductance of about 1.2nH, producing a 12V transient. In practice, at these high di/dt levels, only chip-scale packaging is practical with Kelvin connections to the gate and source for the gate drive. Driving the gate with a negative voltage for the off-state helps when some inductance cannot be avoided. In real circuits such as push-pull or full-bridges in inverters or motor control, two low-side devices often share a common return for source and gate drive current, as shown in Figure 3.
Fig. 3: Low-side devices sharing common grounds
Now, Kelvin connections are not possible because there are two drivers, each with its own return. The two driver grounds and two emitter (source) connections must be connected together. If this connection point is physically located at Powergnd 1, near the left-hand switch, the right-hand switch will experience greater source connection inductance than the left. This results in asymmetrical switching, potential EMI, and possible damage due to induced voltages across the inductance.
For symmetry, the point 'Powergnd 2' is the only viable option, but it remains a poor compromise. In this configuration, both sources have equal—but large—connection inductances in the gate drive loop, especially in high-power electronic systems where the devices may not be physically close together. A solution is to provide isolated signals and power supplies to the two gate drivers as shown in Figure 4. This is often achieved using a gate driver DC/DC converter. Now the driver signal and power returns can connect directly to their respective device emitters (sources), excluding most external inductances from the drive loops.
Fig. 4: Gate drives incorporating signal and power isolation with Kelvin connections
