To better understand how 3DPP and other advanced packaging techniques drive continuous miniaturization of DC/DC converters, it is prudent to dig a little deeper into various packaging practices along with advancements in component technology.
Combining previously disaggregated components into a single assembly is not a new concept, but the methodologies have advanced greatly over the last couple decades. In
power solutions, an integrated module typically referred to a classic, discrete implementation with components tightly-packed on a thin piece of FR-4 (a.k.a. – PCB), then covered with some kind of plastic or metal cap. The caps were mostly for aesthetics to give the illusion of being a single, IC-like assembly though the metal cap could also serve a practical purpose in terms of electromagnetic interference (EMI) and/or thermal mitigation.
Then along came a push for actual process integration of all these disaggregated components into what is now known as heterogeneous integration. A definition of heterogeneous integration from the Institute of Electrical and Electronics Engineers (IEEE) Electronics Packaging Society (EPS) Heterogeneous Integration Roadmap (HIR) is as follows –
“Heterogeneous Integration refers to the integration of separately manufactured components into a higher level assembly that, in the aggregate, provides enhanced functionality and improved operating characteristics.” [4]
The HIR was the culmination of numerous stakeholders, industry leaders, and proceedings from workshops and conferences characterizing the state-of-the-art (SOTA) in this space. While a comprehensive overview of this effort is outside the scope of this
blog article, a handful of key drivers specific to power converters/solutions is noteworthy here. Recall the push for optimizing SWaP factors as outlined up at the beginning of this discussion. While the desire to reduce size/weight may be more tangible, the drive for increasing power density and the strategies for accomplishing that goal may be less obvious.
In most switching power topologies (i.e. – those using carefully-controlled switches to modulate power conversion from one voltage to another), the key figure of merit (FOM) driving size is related to the switching frequency of the power converter. In order to avoid outlining a series of equations charting the mathematical relationships between converter design/component calculations and switching frequency, which a simple Google search will yield copious amounts of input on, there a couple rules-of-thumb to consider here. Switching frequency is inversely proportional to the size of
energy storage and filter components (i.e. - transformers, inductors, toroids, chokes, bulk/electrolytic caps, safety caps, etc.), which often dominate the overall size/weight of power supply (and even be a primary contributor to whole system size/weight).
Parasitic effects of inductance from longer interconnects and fast current transitions [v(t)=L*di/dt] induced by higher switching frequencies can cause catastrophic voltage spikes (a.k.a. – transients) to a converter’s control scheme and/or power train. Parasitic effects of capacitance from the natural separation of conductors in a system and fast voltage transitions [i(t)=C*dV/dt] induced by higher switching frequencies can cause catastrophic energy storage and circulating currents that can rear their ugly heads in any number of undesirable ways.
The growing use of wide bandgap (WBG) power semiconductors (i.e. –
gallium nitride or GaN,
silicon carbide or SiC, etc.) in power electronics designs provides the best and worst of both worlds. WBG devices have the ability to offer significant increases in switching frequency along with greater thermal FOMs (enhancing reliability and power density), but may also come with a steep learning curve that complements their improved power density FOMs. While out of the scope of this blog, it should be noted even just the
gate driver circuits for WBG devices can be far more complex due to increased switching speeds and transients that are a departure from the design rules for traditional, silicon power semiconductors [5]. An excellent overview and reference to such challenges can be found in our
whitepaper "DC/DC Converters for GaN Gate Drivers". Though certainly a deeper topic for a future discussion, it should be noted advancements in high-frequency magnetics materials are a critical enabler for WBG-based solutions and have received focused attention in the last decade due to a research gap in this space (reference some free workshop proceedings at the bottom of this website).
Now that there is a much better understanding of the need for reducing package size, packaging-induced parasitics, and support for the SOTA in semiconductors, the focus can shift to other components that can be beneficial and enabling to heterogeneous integration in
3DPP products. Shrinking the overall power solution also means shrinking the other active (i.e. – ICs, switches) and passive devices (i.e. – resistors, capacitors, inductors, diodes) and bringing them closer together by embedding them in a heterogeneous arrangement. At some point, even the internal package interconnects (i.e. – pins, bumps, pads, etc.) become prohibitive and induce undesired parasitics. There are numerous technologies that allow the embedding of both passive and active devices. While not deep-diving here, it should be noted the utilization of planar magnetics has been hugely enabling. This refers to the transition of a traditional magnetic, with wiring physically wound around a bulky magnetic core, to using PCB traces routed around magnetic core material for a much cleaner, tightly-controlled, yet repeatable and robust magnetic component. [6]
